1. Field of the Invention
The invention relates to computer clocking systems, and more particularly, to methods of and devices for correcting edge placement errors, both positive and negative, during the coasting phases in multiplying phase-locked loops to generate local system clock signals from master clock signals.
2. Description of the Related Art
In efforts to realize greater computing power, microprocessor developers have continuously pushed the clock speeds ever higher. As few as ten years ago, microprocessor clock frequencies of 16 MHz were rare. Today, one sees microprocessors running at frequencies of 50 MHz and even higher.
With these higher clock frequencies have come concurrent problems. Distribution of a 50 MHz clock to the various components of a digital computer system can present difficulties associated with electromagnetic interference (EMI), clock skew, and reflections of the higher harmonics of the system clock signal. Transmission of high frequency clock signals over connectors to companion boards exacerbates these problems.
Developers have sought creative solutions to these problems. One approach has been to rely on a lower frequency system clock, and then generate, on the microprocessor or peripheral chip itself, a higher frequency clock signal from that lower frequency system clock. A number of current microprocessors and peripheral chips implement such a technique, for example, the 80486DX2 by Intel Corporation. This technique has the advantage of increasing a chip's internal processing rate without requiring a corresponding increase in system clock frequency, thus avoiding the problems associated with those higher clock rates.
To generate these higher frequency internal clock signals, these chips typically use a phase-locked loop (PLL) configured as a frequency multiplier. A block diagram of such a frequency multiplier circuit is shown in FIG. 1. As is shown, a phase detector (or phase comparator) drives, through a filter, a voltage controlled oscillator (VCO). The output of that VCO, which becomes the output signal, is then divided by the desired multiplication factor, and then the phase detector compares that divided reference signal with the input signal. This feedback arrangement compensates for shifts in the phase and frequency of the input signal by a level shift to the VCO, and the output signal is thus synchronized to the input signal. Examples of PLLs that can be configured as frequency multipliers include the CD4046A by RCA Corporation and the 74LS297.
The phase detector has two main purposes. First, it forces the VCO to shift frequencies when the reference signal and the input signal are of different frequencies. Second, it forces slight corrections to the VCO output when the reference and input signals are of the same frequency but are slightly out of phase. Both of these functions are accomplished by adjusting the frequency of the VCO; it is simply a difference of the magnitude of the adjustment.
Multiplying PLL's, however, have certain characteristics that can cause their own problems. In a multiplying PLL the synchronizing frequency is less than the clock signals used as outputs of the PLL. For example, in a multiply by four PLL, the input and synchronizing frequency may be 12.5 MHz, but a 50 MHz output frequency may be used. This means that four cycles of the output signal will pass before the next synchronizing edge. During this period the PLL is considered to be coasting. The synchronizing signal may be exactly locked onto the input signal, but the output signal may have some drifts during the coasting period. For example, while the total number of cycles in the coasting period may be the multiplying factor, the location of the particular rising and falling edges defining the output signal cycles during the coasting period may not be exactly the same. For example, some cycles may be slightly longer than others, resulting in a slight wobble or dither during the coasting period. These errors are referred to as edge placement errors. Additionally, there may also be duty cycle variations. These problems increase, relatively, as the multiplying factor and PLL frequency increase. As an example, in the PLL of the preferred embodiment, a 12.5 MHz input clock is used, with 25 and 50 MHz outputs. Referring to the 50 MHz output, the 80 ns coasting period results in four 20 ns cycles of the 50 MHz signal. In certain observations without the use of the present invention, the four cycles actually had lengths of slightly more than 20 ns, slightly more than 19 ns, slightly more than 20 ns and slightly more than 19 ns, the total being 80 ns, but the individual cycles varying from the ideal 20 ns by as much as 3-5%.
Microprocessors and their support chips typically have minimum and maximum allowable clock input frequencies, duty cycles and cycle to cycle tolerances. For example, the 80486DX-50 microprocessor from Intel Corporation requires the clock period stability to be within 0.1%. The duty cycle is similarly critical, with a minimum time of 7 ns at high and 7 ns at low signal levels, with transitions being less than 2 ns each. This means that the duty cycle variability in a 50 MHz system having a 20 ns cycle time is very minor and must be very close to 50%.
This very tight tolerancing, particularly the adjacent clock 0.1% value, results in problems when used with a multiplying PLL such as the one described above where the adjacent clock variations may reach 5%. Some solution is needed to reduce the adjacent clock variations to acceptable levels.